Anton Blanchard
Fellow at Tenstorrent
Greater Sydney Area Australia
Summary
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RockstarAnton Blanchard is a seasoned systems engineer and Fellow with 26 years of experience building high-performance software for CPUs, kernels, and EDA flows, now based in Greater Sydney. He spent two decades at IBM as a Linux kernel hacker and Distinguished Engineer and now applies that low-level expertise at Tenstorrent. Anton is an active open-source contributor to prominent projects such as the Julia language and OpenROAD/OpenLane, where he focused on architecture support, LLVM backend fixes, and routing/timing optimizations. His work shows a rare combination of kernel internals, CPU microarchitecture (Microwatt), and electronic design automation performance tuning. Notably, he has deep PowerPC expertise—patching LLVM, improving PowerPC64 JIT and endian handling, and hardening timer and memory subsystems. Pragmatic and detail-oriented, he removes long-standing workarounds by driving fixes upstream rather than piling on bandaids.
26 years of coding experience
11 years of employment as a software developer
Github Skills (51)
powerpc10
verilog10
c-language10
assembly10
back-end-development10
python10
computer-architecture10
architecture10
llvm10
testing10
linux10
c1110
linux-kernel10
c1710
vhdl10
Programming languages (17)
Github contributions (5)
antonblanchard/microwatt
Aug 2019 - Nov 2022
A tiny Open POWER ISA softcore written in VHDL 2008
Role in this project:
Back-end Developer
Back-end DeveloperContributions:512 commits, 349 PRs, 311 pushes in 3 years 3 months
Contributions summary:Anton made numerous contributions to the `microwatt` repository, focusing on enhancements to the processor's execution pipeline and instruction set. These contributions include the addition of new instructions, such as `srd` and `srw`, and implementing significant refactoring of existing components, like `decode2`. Moreover, the user focused on fixing and improving the internal code structure of the project and also on performance improvements related to pipeline, memory, and core system-on-a-chip operation.
ppc64leisavhdltinypower
The-OpenROAD-Project/OpenLane
Dec 2020 - Jan 2023
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Role in this project:Backend & Automation Engineer
Backend & Automation EngineerContributions:11 reviews, 70 commits, 76 PRs in 2 years 1 month
Contributions summary:Anton primarily contributed to the OpenLane project by making improvements to the automated RTL to GDSII flow, specifically focusing on routing and timing optimization. Their commits involved modifying Tcl scripts to enhance the routing process, address manufacturability issues, and improve timing analysis. They also made fixes related to the ECO flow, improving buffer insertion and STA integration. Furthermore, they optimized the performance of the antenna violation script.
rtlfoundrymagicmethodologyvlsi
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