Aporva Amarnath
Senior Member Of Technical Staff at AMD
California, United States
Summary
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Senior🎓
Top SchoolAporva Amarnath is a Senior Member of Technical Staff at AMD RAD in California with a decade of experience building heterogeneous systems, runtimes, and architecture-level optimizations. She holds a PhD in Electrical and Computer Engineering from the University of Michigan and has transitioned research into industry roles at IBM and AMD, focusing on schedulers, load-store unit optimizations, and power-efficient designs for HPC and exascale workloads. Her background spans VLSI circuit design at NVIDIA to system-level architecture research, giving her a rare cross-layer perspective from transistor-level memory design to runtime scheduling. Notably, her work has targeted reducing dynamic power and performance variability through architectural mechanisms and partitioning strategies for load queues. Colleagues describe her as an engineer who bridges rigorous academic research with practical, production-oriented solutions in heterogeneous computing.
10 years of coding experience
9 years of employment as a software developer
BITS Pilani, Birla Institute of Technology and ScienceDoctor of Philosophy - PhD Electrical and Computer Engineering, Doctor of Philosophy - PhD Electrical and Computer Engineering at University of Michigan
English, Hindi, Telugu
Github Skills (10)
heterogeneous10
performance-analysis10
agile10
meta9
optimization9
stomp9
workload7
scheduling7
scheduler6
golang5
Programming languages (2)
Github contributions (5)
IBM/stomp
Jul 2019 - Sep 2022
STOMP: Scheduling Techniques Optimization in heterogeneous Multi-Processors
Contributions:103 commits, 1 PR, 30 pushes in 3 years 2 months
techniquesschedulingheterogeneousprocessorsoptimization
augustojv/epochs-tutorial-2024
Mar 2024 - Sep 2024
Contributions:14 pushes in 6 months
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