Arild Velure
Principal FPGA Developer at Velure Design Bureau
Bergen, Vestland, Norway
Summary
👤
Senior🎓
Top SchoolArild Velure is a Principal FPGA developer with 11 years of hands-on experience designing, verifying and deploying advanced FPGA and ASIC systems for space and high-energy physics applications. He combines deep RTL verification expertise with practical analog/digital hardware skills, PCB/layout and design-for-manufacturing know-how, gained through roles at Inventas, CERN and in medical-device engineering. As a tech lead he has overseen multiple space projects, built continuous-integration flows with hardware-in-the-loop, and served as sole verification engineer on complex low-power ASIC and FPGA efforts. Holding a PhD in microelectronics and experimental physics from the University of Bergen, he brings a research-grade attention to test and verification while also shipping production-ready hardware. Notably, his background bridges high-speed DAQ system design and hands-on production/testing, making him effective across the full hardware lifecycle.
10 years of coding experience
3 years of employment as a software developer
Master of Science (M.Sc.), Microelectronics/Physics, Master of Science (M.Sc.), Microelectronics/Physics at Universitetet i Bergen (UiB)Doctor of Philosophy (PhD), Microelectronics/Nuclear Experimental Physics/Physics, Doctor of Philosophy (PhD), Microelectronics/Nuclear Experimental Physics/Physics at University of Bergen (UiB)Bachelor of Science (B.Sc.), Electronic Engineering, Bachelor of Science (B.Sc.), Electronic Engineering at Høgskolen i Bergen (HiB)
English, Norwegian, French
Github Skills (37)
simulator10
hardware10
gcc10
vhdl10
ghdl10
compile10
doxygen10
testbench10
git-repository9
simulation9
beautify9
swig9
flexlm9
fpga9
compiler8
Programming languages (6)
Github contributions (5)
avelure/doxygen-verilog
Dec 2015 - Feb 2018
Contributions:21 commits, 10 pushes, 1 branch in 2 years 2 months
git-repositorydoxygen
avelure/UVVM_All
Jan 2018 - Oct 2024
Contributions:5 pushes, 1 branch in 6 years 10 months
asicstructuredvhdlcomponent-frameworkverification
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