Arit Ghosh
FPGA Validation Engineer At AMD, Hyderabad
Alipurduar, West Bengal, India
Summary
👤
Senior🎓
Top SchoolArit Ghosh is an FPGA Validation Engineer at AMD in Hyderabad with a strong VLSI foundation from NIT Agartala and 11 years of diverse technical and operational experience. Early work at Cadence honed his C++, Python, TCL/TK, Verilog and RTL skills while contributing to Tempus timing-closure features and STA automation. He pairs hands-on FPGA validation know-how with practical systems experience gained in roles ranging from embedded C development to terminal management, showing an ability to bridge engineering and operational constraints. Arit’s background suggests a knack for turning complex timing and verification challenges into repeatable automated flows. Based in Alipurduar, he brings both academic rigor and real-world problem-solving to high-performance hardware teams. Colleagues can expect an engineer comfortable across software, RTL and validation disciplines who values automation and measurable improvements.
11 years of coding experience
1 year of employment as a software developer
Bachelor of Technology, Electronics and communication engineering, A, Bachelor of Technology, Electronics and communication engineering, A at Assam (Central) UniversityHigher Secondary, Science Stream, A+, Higher Secondary, Science Stream, A+ at Sonapur B K High school(HS)M. Tech, VLSI Design, 8.48, M. Tech, VLSI Design, 8.48 at National Institute of Technology Agartala
English, Bengali, Hindi
Github Skills (6)
civicrm5
php4
drupal4
entity4
audio3
react1
Programming languages (1)
Github contributions (5)
shrimala/ahsweb
Aug 2015 - Aug 2016
Contributions:957 commits, 137 PRs, 1467 pushes in 11 months
aritnath1990/media_migration
Mar 2016 - Aug 2016
Contributions:2 PRs, 45 pushes, 13 branches in 4 months
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