Arjan Bink - Distinguished Engineer - IC Design at Silicon Labs

Arjan Bink

Distinguished Engineer - IC Design at Silicon Labs

Oslo, Norway

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Summary

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Rockstar

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Top School

Arjan Bink is a Distinguished Engineer and chip architect with over two decades of hands-on experience designing low-power SoCs, microcontrollers and RISC-V cores, now leading IC architecture for Silicon Labs' Wireless Gecko IoT platforms. He blends deep RTL and verification expertise (VHDL/Verilog/SystemVerilog, SystemC/TLM) with practical production skills from FPGA prototyping to STA and mixed-mode silicon bring-up, and has driven power management, clocking and bus-level security across multiple product generations. An active open-source contributor and former Chair of OpenHW’s Cores Task Group, he has authored and architected open RISC-V cores (CV32E40x) and contributed verification and test automation to widely used OpenHW repositories. Colleagues rely on him for pragmatic architecture decisions that span IP, integration and customer support, and he’s known for translating complex low-power constraints into manufacturable silicon. Based in Oslo, he pairs academic foundations in computing science with a rare combination of leadership, tooling fluency and deep silicon-level curiosity.

6 years of coding experience

25 years of employment as a software developer

PDEng Software Technology, PDEng Software Technology at Eindhoven University of Technology

Github Skills (21)

systemverilog10

cpu10

risc-v10

verification10

asic10

digital-design10

sys10

systemverilog-hdl10

hdl10

embedded10

test-automation10

uvm9

automation9

automations9

fpga9

Programming languages (8)

SystemVerilogCMakefileTeXVerilogHTMLAssemblyPython

Github contributions (5)

openhwgroup/cv32e40p

Mar 2020 - Mar 2022

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Role in this project:

Embedded Systems Engineer / IoT Developer

Contributions:2 releases, 134 reviews, 201 commits in 2 years

Contributions summary:Arjan's contributions center around the CV32E40P, an in-order RISC-V CPU, with a focus on parameter and pinout cleanup and the addition of features. They made modifications to the core's architecture, including changes to CSR address spaces, register files, and test benches, as well as re-adding and configuring the APU interface. Moreover, the user updated and adjusted test cases to align with the current hardware configurations and removed obsolete test suites.

risc-vcpupulpuvmriscv

openhwgroup/core-v-verif

Sep 2020 - Dec 2022

Functional verification project for the CORE-V family of RISC-V cores.

Role in this project:

Test Automation Engineer

Contributions:24 reviews, 12 commits, 16 PRs in 2 years 3 months

Contributions summary:Arjan primarily contributed to the functional verification of a RISC-V core, focusing on the `openhwgroup/core-v-verif` repository. Their commits involve modifying test benches and test programs written in SystemVerilog and C, specifically targeting performance counter tests and hazard scenarios. The changes include adding and modifying test scenarios, fixing bugs, and adapting the code to the latest RTL updates.

risc-vsystemverilogriscverificationcores

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