Ashutosh Sahoo
Associate Staff Engineer
Odisha, India
Summary
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Top SchoolAshutosh Sahoo is an Associate Staff Engineer with a strong 8-year track record in VLSI design and functional verification, currently leading system-bus, MCU subsystem and peripheral protocol verification at Samsung Semiconductor. He specializes in SystemVerilog-UVM testbench architecture, scoreboard/checker development, coverage closure and security feature validation for SoCs, and has built driver-sequencer/monitor handshakes and scoreboards from scratch. His background includes hands-on RTL programming and emulator-compatible VIP verification, with prior experience on AMBA AHB and training on TL-Verilog RISC-V cores that improved code efficiency by 60–70%. A NIT Rourkela alumnus and VLSI enthusiast, he blends rigorous testplan-driven verification with practical emulation and scripting skills to accelerate silicon readiness.
7 years of coding experience
3 years of employment as a software developer
Matriculation, Matriculation at D.A.V. Public School, Pokhariput, Bhubaneswar, OdishaBachelor of Technology - BTech Electronics and Instrumentation Engineering, Bachelor of Technology - BTech Electronics and Instrumentation Engineering at National Institute of Technology Rourkela12th Physics Chemistry Mathematics, 12th Physics Chemistry Mathematics at Mother's Public School, Bhubaneswar, Odisha Github contributions (5)
RISCV-MYTH-WORKSHOP/RISC-V-CPU-Core-using-TL-Verilog
Aug 2020 - Sep 2020
Contributions:267 commits, 9 pushes in 20 days
Contributions:7 pushes, 1 branch in 6 days
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