Aswin Venkatesh
ASIC Engineer at Cisco
San Jose, California, United States
Summary
👤
Senior🎓
Top SchoolAswin Venkatesh is an ASIC/RTL design engineer with 8 years of experience driving microarchitecture, RTL implementation, FPGA prototyping, and silicon bring-up for sensor SoCs. He has led the design and delivery of an in-house 32-bit microprocessor IP (eDMP), serial interface and sensor controller IPs, and explored custom hardware accelerators for motion algorithms and ML workloads. Comfortable across the full RTL flow—simulation, verification, STA, formality, and metal ECOs—he pairs hardware design with system-level FPGA emulation and cross-functional bring-up. At TDK InvenSense he managed small FPGA teams and collaborated closely with software groups to tune ISAs for performance and code density, a pragmatic habit he continues at Cisco. Beyond work he hacks and modifies hardware, contributes to open-source projects, and brings a hands-on curiosity that surfaces in both silicon fixes and prototyping.
8 years of coding experience
8 years of employment as a software developer
Bachelor’s Degree Electrical and Electronics Engineering, Bachelor’s Degree Electrical and Electronics Engineering at Anna University, ChennaiMaster's degree Electrical and Computer Engineering, Master's degree Electrical and Computer Engineering at Stony Brook University
Malay, Tamil, English
Stackoverflow
1reputation
0reached
0answers
0questions
Github Skills (5)
campus6
genetic5
infrastructure2
hugo1
hugo-theme1
Programming languages (1)
Github contributions (5)
Aswinnatesh/common_scripts
Jan 2021 - Mar 2025
Contributions:4 pushes in 4 years 1 month
Aswinnatesh/Synergistic-Processing-Unit-of-Sony-Cell
Mar 2018 - Mar 2020
Contributions:6 pushes, 1 branch in 1 year 11 months
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