Audrey Kertesz
Senior Principal Engineer at Tenstorrent
Calgary, Alberta, Canada
Summary
🤩
Rockstar🎓
Top SchoolAudrey Kertesz is a Senior Principal Engineer based in Calgary with five years of focused experience accelerating FPGA-based AI and networking solutions across startups and Intel. She has led teams and product architecture for FPGA compilers and high-level design tools, invented techniques to enable higher-precision DNN layers on FPGA inference engines, and shipped P4-to-FPGA compiler technology for packet processing. Audrey’s recent roles at Untether AI and Tenstorrent highlight a shift into cutting-edge AI accelerator engineering while her open-source contributions to Intel’s oneAPI FPGA samples show hands-on optimization for performance-critical designs like GZIP and CRR solvers. She pairs deep device-level CAD and RTL knowledge with software and systems leadership, and is notable for scaling junior teams to production-capable device bring-up. Academically grounded with an M.A.Sc. from the University of Toronto, she blends rigorous research instincts with pragmatic product delivery.
5 years of coding experience
12 years of employment as a software developer
Master of Applied Science (M.A.Sc.) Electrical and Electronics Engineering, Master of Applied Science (M.A.Sc.) Electrical and Electronics Engineering at University of TorontoBachelor's Degree Electrical Engineering Biomedical Specialization, Bachelor's Degree Electrical Engineering Biomedical Specialization at University of Calgary
Github Skills (10)
fpga10
sycl10
dpc10
oneapi10
c-language10
cprogramming-language10
performance-optimization10
loop-unrolling9
gzip8
cuda4
Programming languages (3)
Github contributions (5)
oneapi-src/oneAPI-samples
Aug 2020 - May 2021
Samples for Intel® oneAPI Toolkits
Role in this project:
Backend Developer
Backend DeveloperContributions:88 reviews, 31 commits, 103 PRs in 9 months
Contributions summary:Audrey's commits primarily involve the development and implementation of FPGA code samples, specifically for Intel's oneAPI toolkits. The contributions focus on the CRR solver, the addition of FPGA register and loop unroll tutorials, and updates related to Beta10 compatibility and performance enhancements for the GZIP reference design, including USM for data transfer. These contributions involved implementing and optimizing the code samples for the FPGA architecture.
numbatoolkitsswrepoaplpower-management
akertesz/oneAPI-samples
Aug 2020 - May 2021
Samples for Intel oneAPI toolkits
Contributions:51 pushes, 85 branches in 9 months
tlaintelintel-oneapi-toolkitsoneapitoolkits
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