Aurélien Tran
Responsible For SSD Memory Engineering Development at Toshiba Corporation
Yokohama, Kanagawa Prefecture, France
Summary
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Senior🎓
Top SchoolAurélien Tran is an SSD memory engineering lead with 11+ years designing next-generation storage systems at Toshiba, combining deep firmware, SOC and hardware expertise. He specializes in C/C++, Python, multi-core processor programming (including Cell and MEP architectures), VHDL and Linux, and has driven SSD firmware and SOC methodology work across France and Japan. Educated in microelectronics (ESIEE Paris), he pairs academic rigor with practical R&D experience from university projects to corporate product development. Based in Yokohama, he brings a cross-cultural engineering perspective and a track record of translating low-level hardware constraints into robust, production-ready storage solutions.
11 years of coding experience
3 years of employment as a software developer
Master's degree, Microelectronics, Master's degree, Microelectronics at ESIEE PARIS
english (toeic 910), Japanese, French
Github Skills (3)
testing7
gameboy3
emulation2
Programming languages (1)
Github contributions (5)
AurelienTran/GameBoyPlay
Feb 2015 - Jun 2015
Contributions:61 commits, 1 PR, 31 pushes in 4 months
gameboyemulatoremulationgameboy-emulator
AurelienTran/DeepLearning
Jul 2019 - Sep 2019
Contributions:1 release, 32 commits, 23 pushes in 1 month
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