Ayush Maheshwari
Senior Silicon Design Engineer at AMD
Jaipur, Rajasthan, India
Summary
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Top SchoolAyush Maheshwari is a Senior Silicon Design Engineer with eight years of experience in high-performance memory and verification work, currently at AMD after roles at Analog Devices and Samsung. He has hands-on expertise in DDR5 behavioral modeling, BCH ECC C++ modeling, SystemVerilog FIFO design, and formal verification of sub-modules, bridging implementation and verification workflows. Ayush pairs strong academic credentials—a BTech with a 9.3 CGPA and ongoing MTech studies at BITS Pilani—with practical industry delivery across IP development and verification teams. He has also taken campus leadership roles coordinating placements and internships, showing an aptitude for cross-functional coordination and talent development. Based in Jaipur, he brings a blend of rigorous technical depth and pragmatic problem-solving, often turning complex verification needs into automated, auditable solutions. Colleagues would note his curiosity-driven approach to “exploring tech,” reflected in diverse tooling from C++ models to SystemVerilog assertions.
7 years of coding experience
4 years of employment as a software developer
BITS Pilani, Birla Institute of Technology and ScienceBachelor of Technology - BTech, Electrical, Electronics and Communications Engineering, CGPA 9.3, Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering, CGPA 9.3 at National Institute of Technology Kurukshetra
English, Hindi, MarwariProgramming languages (2)
Github contributions (5)
ayushmaheshwari768/Projects-1
May 2021 - Jun 2022
Contributions:7 pushes in 1 year
ayushmaheshwari768/CIS24C
Jun 2018 - Jul 2018
Contributions:17 pushes in 1 month
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