Bea Healy
PhD Candidate
Cambridge, England, United Kingdom
Summary
🤩
Rockstar🎓
Top SchoolBea Healy is a PhD candidate in Computer Science based in Cambridge with roughly four years of hands-on experience bridging hardware, compilers, and formal verification. She has contributed to major open-source EDA tooling—most notably enhancing the Yosys synthesis suite with register file mapping, custom primitives, and flow integrations for FABulous—while working on FPGA fabric generation and bitstream tooling across Manchester and Edinburgh research projects. Her work combines practical engineering (CI, Docker, scripting) with research outputs presented at FPGA-focused venues, and she has taught advanced computer architecture to undergraduates. Bea’s background in managing technical teams and festival-scale equipment operations reveals a pragmatic problem-solver comfortable both in lab codebases and real-world logistics.
4 years of coding experience
1 year of employment as a software developer
Doctor of Philosophy - PhD, Informatics, Doctor of Philosophy - PhD, Informatics at The University of EdinburghBachelor of Engineering - BE, Computer Systems Engineering, First Class with Honours, Bachelor of Engineering - BE, Computer Systems Engineering, First Class with Honours at The University of ManchesterDoctor of Philosophy - PhD, Computer Science, Doctor of Philosophy - PhD, Computer Science at University of CambridgeHayesfield Mixed Sixth Form
English, French, Italian
Github Skills (4)
yosys10
scripting10
verilog10
makefile7
Programming languages (7)
Github contributions (5)
YosysHQ/yosys
Sep 2022 - Sep 2022
Yosys Open SYnthesis Suite
Role in this project:
Back-end Developer
Back-end DeveloperContributions:7 commits in 2 days
Contributions summary:Bea focused on enhancing the Yosys Open SYnthesis Suite by introducing and refining functionalities related to hardware synthesis. Their work involved implementing register file mappings, modifying the synthesis flow, and incorporating custom primitive libraries. The user re-introduced and corrected flags for a FABulous VPR flow which involved code changes within synthesis scripts and the addition of a new script pass.
synthesispythonsuiteyosys
FPGA-Research/FABulous
Aug 2021 - Jan 2023
Fabric generator and CAD tools
Contributions:22 reviews, 173 commits, 90 PRs in 1 year 5 months
vivadocadfabricedafpga
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