Ben Reynwar
Freelance RTL Engineer Funbbatical
Tucson, Arizona, United States
Summary
👤
Senior🎓
Top SchoolBen Reynwar is a versatile RTL and software engineer with 15 years of experience building FPGA and ASIC designs, simulators, and production-ready tooling from Tucson, Arizona. He has driven LDPC encoder/decoder architectures through FPGA prototyping to front-end ASIC estimates, implemented a SystemVerilog accelerator for Fully Homomorphic Encryption, and set up robust CI with cocotb and VUnit. An active open-source contributor, he has improved test suites and back-end reliability for notable projects like the GHDL VHDL simulator and the FuseSoC package manager. Ben’s background spans academia (a PhD in chemical engineering) to startups and research institutes, giving him a rare blend of deep modelling, hardware implementation, and practical software automation skills. He’s currently freelance and selectively pursues fun or impactful contract and open-source projects—often surfacing subtle bugs and improving testability and maintainability behind the scenes.
15 years of coding experience
16 years of employment as a software developer
Ph.D., Chemical Engineering, Ph.D., Chemical Engineering at University of California, BerkeleyB.E., Chemical and Process Engineering, B.E., Chemical and Process Engineering at University of Canterbury
Github Skills (25)
verilog10
python10
simulator10
document-generation10
eda10
vhdl10
package-manager-tool10
ghdl10
fpga10
doxygen10
package-manager10
testbench10
documents10
swig10
documentation10
Programming languages (13)
Github contributions (5)
olofk/fusesoc
Mar 2017 - Jul 2020
Package manager and build abstraction tool for FPGA/ASIC development
Role in this project:
Back-end Developer
Back-end DeveloperContributions:13 commits, 10 PRs, 42 comments in 3 years 3 months
Contributions summary:Ben primarily focused on refactoring and improving the codebase of a package manager and build abstraction tool for FPGA/ASIC development. Their work involved replacing legacy logging methods with the standard logging module, enhancing code maintainability. The user also addressed several bugs and edge cases within the core files related to generator functionalities. Furthermore, they improved the handling of core file errors and improved file order, ensuring more reliable and organized processes.
asicpythonvhdledapackage-manager
ghdl/ghdl
May 2020 - May 2020
VHDL 2008/93/87 simulator
Role in this project:QA Engineer / Test Automation Engineer
QA Engineer / Test Automation EngineerContributions:6 commits, 8 PRs, 44 comments in 9 days
Contributions summary:Ben primarily focused on enhancing the test suite for the GHDL simulator. They implemented new tests for VPI (Verilog Procedural Interface) to ensure correct access to constants, including enum and array types. The user also added a regression test that compares generated waveform dumps, demonstrating a commitment to maintaining the integrity of the simulation results over time. Additionally, they addressed an issue with zero-length signals in the dumping functionality.
vhdlsimulationghdlcompilersimulator
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