Bhargav Sriram is a Senior CAD Engineer with a decade of engineering experience, currently supporting multiple chip tape-outs at Marvell and developing physical design CAD flows for cutting-edge TSMC 3nm and 2nm nodes. He has hands-on expertise in PPA analysis, floorplan-driven area reduction (including a 20% block area win), IR-drop mitigation, and automation with Python to compare metrics across advanced nodes. His background blends academic research—working on LSTM and physics-informed neural networks for PV forecasting—with practical EDA tool collaboration, including identifying critical bugs with Cadence representatives. Comfortable across hierarchical top-down physical design and block integration, he brings an uncommon mix of power-aware optimization and scripting-driven workflow improvements. Based in New York, he pairs Columbia graduate training with proven tape-out support experience in a high-volume semiconductor environment.
10 years of coding experience
High School Diploma, Mathematics and Computer Science, High School Diploma, Mathematics and Computer Science at Chettinad Vidyashram
B.Tech, Electrical and Electronics Engineering, B.Tech, Electrical and Electronics Engineering at Vellore Institute of Technology
Master of Science - MS, Electrical and Electronics Engineering, Master of Science - MS, Electrical and Electronics Engineering at Columbia University
Contributions:4 pushes, 1 branch in 1 year 4 months
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Bhargav Sriram - Senior CAD Engineer at Marvell Technology