Bhashitha Adhikarinayake is an R&D engineer with 9 years of experience building high-performance, time-critical systems for computer hardware and verification tooling. Based in San Jose, he has driven compiler and runtime implementations that accelerate Verilog simulation on GPUs and FPGAs using CUDA/C++, and now extends toolchains with LLM-enabled Neovim and VSCode integrations. He combines a strong academic foundation in Electronic and Telecommunication Engineering (First Class, University of Moratuwa) with hands-on expertise in low-level parallel software, risk calculation libraries, and developer tooling across C++, Python, TypeScript, and Lua. Known for turning hardware-focused research into production-grade software, he blends systems-level depth with practical UX improvements for verification engineers.
9 years of coding experience
8 years of employment as a software developer
Bachelor of Science of Engineering, Electronic and Telecommunication Engineering, First Class (3.73/4.2), Bachelor of Science of Engineering, Electronic and Telecommunication Engineering, First Class (3.73/4.2) at University of Moratuwa
Seventhday Adventist High School
High School, Physical Sciences, High School, Physical Sciences at Thurstan College
Nvim Treesitter configurations and abstraction layer
Contributions:7 pushes in 1 year
luanvim-treesittertreesittervimneovim
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Bhashitha Adhikarinayake - R&D Engineer, Sr II at Synopsys Inc