Bill Mcspadden
Formal Verification Engineer
Chanhassen, Minnesota, United States
Summary
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Rockstar🎓
Top SchoolBill Mcspadden is a Formal Verification Engineer with over four decades of hands-on experience in digital design and verification, currently focused on building and maintaining the formal model of the RISC-V processor and its ratified extensions. He has a deep legacy across industry leaders—from early chipset and processor work at Intel to principal verification roles at Seagate and Starkey—and now plays an active role in the open RISC-V ecosystem, including leadership in the Architectural Test SIG and contributions to instruction trace, fast interrupt, cache management, and virtual memory groups. Known for bridging low-level hardware intricacies with rigorous verification methods, he brings practical expertise in Verilog/SystemVerilog, OVM/UVM, and microprocessor validation. Based in Chanhassen, Minnesota, Bill combines institutional memory from large-scale silicon projects with current open-source collaboration, making him a rare resource who can both codify architecture specifications and verify their implementation.
4 years of coding experience
34 years of employment as a software developer
Graduate classes in mathematics and programming, Graduate classes in mathematics and programming at Oregon Graduate Institute of Science and TechnologyBachelor’s Degree, Electrical Engineering, Bachelor’s Degree, Electrical Engineering at Texas A&M University
Github Skills (10)
risc-v10
risc10
v-model10
openembedded10
tla8
architecture6
formal-methods5
v-for3
vscode1
vscode-extension1
Programming languages (7)
Github contributions (5)
billmcspadden-riscv/sail-riscv
Aug 2022 - Oct 2024
Sail RISC-V model
Contributions:51 pushes, 12 branches in 2 years 2 months
risc-vriscv-modelsail
billmcspadden-riscv/sail
Feb 2022 - Aug 2023
Sail architecture definition language
Contributions:74 pushes, 1 branch in 1 year 5 months
architecturedefinitionsail
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