Bipul Talukdar
Senior Director Of Engineering at Axiomise
San Jose, California, United States
Summary
🤩
Rockstar🎓
Top SchoolBipul Talukdar is a senior engineering leader with over a decade of hands-on expertise in hardware functional verification, specializing in RISC‑V, Verification IP architecture, formal property verification, emulation, and clock-domain crossing. He has driven verification IP development and application across enterprise tools and startups—shaping flows that blend Chisel-generated RTL, SystemVerilog/UVM, and formal engines to close coverage for complex subsystems. Bipul has led regional application teams, technical strategy, and industry evangelism while delivering VIPs and design IPs for protocols like PCIe, TileLink, AMBA and coherence models such as MESI/MOESI. Notable for bridging research and product, he authored Chisel-based formal verification techniques at SiFive and has deep experience merging formal and simulation coverage for real-world tapeout constraints. Based in San Jose, he combines technical depth with customer-facing leadership, regularly presenting at conferences and guiding integrations across simulation, emulation, and formal toolchains.
9 years of coding experience
24 years of employment as a software developer
Bachelor of Engineering Electronics and Telecommunications, Bachelor of Engineering Electronics and Telecommunications at National Institute of Technology, SilcharBachelor's degree Electrical Electronics and Communications Engineering, Bachelor's degree Electrical Electronics and Communications Engineering at National Institute of Technology SilcharCotton College, Guwahati
English, Hindi, Assamese, Sanskrit, Bengali
Github Skills (4)
chisel9
rocket-chip8
scala8
mcu2
Programming languages (2)
Github contributions (4)
bluespec/Tiny_TCM
Oct 2023 - Feb 2024
Contributions:2 pushes in 4 months
bluespec/mcu-release
Oct 2023 - Feb 2024
A release repository for the mcu class of CPUs
Contributions:3 pushes in 4 months
mcu
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