Bolin Chen
TD Module & Integration Yield Engineer
United States
Summary
👤
Senior🎓
Top SchoolBolin Chen is a TD Module & Integration Yield Engineer at Intel with 11 years of experience bridging academic research and industrial yield improvement. He holds a PhD in Mechanical Engineering from Iowa State University and built deep expertise in printable flexible electronics—designing inkjet-printed thermoelectric generators and 3D-printed supercapacitors while formulating functional inks. Bolin’s background spans postdoctoral work at national labs and the University of Chicago to hands-on quality engineering at BMW, giving him a rare mix of advanced materials science, manufacturing process control, and QA systems experience. At Intel he applies this cross-disciplinary skill set to improve module integration yields, leveraging data analysis and electrochemical knowledge to solve production-scale problems. Known for turning lab-scale inventions into robust, manufacturable solutions, he combines experimental rigor with practical process optimization.
11 years of coding experience
6 years of employment as a software developer
Doctor of Philosophy (PhD), Mechanical Engineering, Doctor of Philosophy (PhD), Mechanical Engineering at Iowa State University
Chinese, English
Stackoverflow
1reputation
0reached
0answers
0questions
Github Skills (105)
editor9
realtime9
steganalysis9
visual-studio9
microsoft9
npm9
visual-studio-code9
react9
electron9
vscode-extension9
typescript9
nodejs9
vscode9
mongodb9
reactive-programming8
Programming languages (7)
Github contributions (5)
bolin-chen/audio-steganalysis-cnn
Aug 2019 - Feb 2021
An audio steganalysis method based on CNN in the time domain.
Contributions:6 commits, 5 pushes, 1 branch in 1 year 6 months
deep-learningmethodaudiodomainsteganalysis
bolin-chen/Stego-Post-processing
May 2019 - Jul 2019
Contributions:7 commits, 4 pushes in 2 months
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