Borja Peñuelas
FPGA Design And Verification Engineer (XFT)
Eu, Normandy, Sweden
Summary
👤
Senior🎓
Top SchoolBorja Peñuelas is an FPGA design and verification engineer with 8 years’ experience delivering high-throughput, low-latency systems for telecommunications, defense-grade 3D RADAR and life-critical medical devices. He blends FPGA/SoC hardware architecture with VHDL/SystemVerilog firmware and embedded C++/C software to deliver end-to-end, reliable systems including custom redundant fiber-optic networks and mixed-signal ADC/DAC front-ends. Comfortable working with engineering-sample silicon (Xilinx, Intel) and advanced PCB materials, he applies signal-integrity, EMC and rigorous RTL/architectural practices to meet safety and MISRA/CERT standards. He augments technical depth with verification automation (UVM plus Python/TCL cross-language simulation tools) and production testbench development to enable hardware-on-the-loop runtime validation. Trained in design thinking, lean project management and coaching, he drives collaborative Agile teams that scale reliability-focused practices across organizations. Based in Normandy (Sweden), he brings a systems-level mindset that anticipates cross-domain interactions between hardware, firmware and software early in the design cycle.
9 years of coding experience
Industrial Engineering Master's Degree, Industrial Engineering Master's Degree at Universidad Católica de ÁvilaCoaching Training, Coaching Training at Grado 3Electronics and Industrial Automation Degree, Electronics and Industrial Automation Degree at Universidad de AlcaláStartup Accelerator Program, Startup Accelerator Program at Impact Hub San FranciscoTelecom Seeds for the Future Training Program, Beijing, China, Telecom Seeds for the Future Training Program, Beijing, China at Huawei UniversityLean Project Management, Lean Project Management at Nestor&Co, H2iDesign Thinking, CA, USA, Design Thinking, CA, USA at Stanford University
English, German, French, Chinese, Spanish
Github Skills (50)
python-social-auth10
diagram10
timing-diagram10
svg10
vscode10
rendering-engine10
systemverilog9
django9
jsonwebtoken9
jwt9
django-rest-framework9
vue-mixin8
esp328
auth-provider8
arduino8
Programming languages (5)
Github contributions (5)
bmpenuelas/wavedrom
Jun 2019 - Apr 2025
:ocean: Digital timing diagram rendering engine
Contributions:5 pushes, 2 branches in 5 years 11 months
rendering-enginesvgoceanrenderingtiming-diagram
bmpenuelas/waveform-render-vscode
Apr 2019 - Dec 2022
Render waveforms inside VSCode with WaveDrom
Contributions:2 releases, 63 commits, 7 PRs in 3 years 9 months
vscode
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