Bradley Morrell
Technical Specialist (Networking) at Sheffield Hallam University
Chesterfield, England, United Kingdom
Summary
🤩
Rockstar🎓
Top SchoolBradley Morrell is a Technical Specialist in Networking with a decade of hands-on IT experience across higher education, enterprise, and SME environments. Currently supporting Sheffield Hallam University, he brings practical frontline troubleshooting from roles at Central Technology Ltd and Dental IT, combined with process and audit experience gained during an internship with Ford. Bradley holds a BSc in Computer Networking and contributes to open-source hardware tooling, having improved TileLink monitoring and formal verification checks in the widely used chipsalliance/rocket-chip project. He blends networking operations, policy-driven improvements, and scripting-friendly engineering—comfortable both as a local SME and a back-end contributor to complex protocols. Colleagues rely on him for methodical problem solving and for turning corner-case issues into robust, verifiable fixes.
10 years of coding experience
5 years of employment as a software developer
Bachelor of Science - BS Computer Networking, Bachelor of Science - BS Computer Networking at Birmingham City UniversityLevel 3 Extended diploma in IT Networks Systems and Cyber Security, Level 3 Extended diploma in IT Networks Systems and Cyber Security at Chesterfield College
Github Skills (5)
formal-verification10
scala10
chisel9
rocket-chip9
rt8
Programming languages (5)
Github contributions (5)
chipsalliance/rocket-chip
Aug 2019 - Nov 2020
Rocket Chip Generator
Role in this project:
Back-end Developer
Back-end DeveloperContributions:8 reviews, 243 commits, 41 PRs in 1 year 2 months
Contributions summary:Bradley primarily worked on the `tilelink` module within the `rocket-chip` repository, modifying the `Monitor.scala` file. They improved the monitoring capabilities of the TileLink protocol by adding tracking for opcodes, sizes and adding assumptions to the monitor to check the messages. The user's work also included fixing corner cases and adding constraints related to the A and D channels of the TileLink protocol. They were also involved in adding features for formal verification using property checking within the monitor.
rtlriscvchipchiselscala
brrmorre/ErrorGoogler
Aug 2020 - Feb 2022
Contributions:280 pushes, 1 branch in 1 year 6 months
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