Brandon Breitenstein

Software Firmware Engineer at Intel Corporation

Hillsboro, Oregon, United States
email-iconphone-icongithub-logolinkedin-logotwitter-logostackoverflow-logofacebook-logo
Join Prog.AI to see contacts
email-iconphone-icongithub-logolinkedin-logotwitter-logostackoverflow-logofacebook-logo
Join Prog.AI to see contacts

Summary

👤
Senior
🎓
Top School
Brandon Breitenstein is a Software Firmware Engineer with 10 years of embedded and firmware experience at Intel, specializing in Chrome OS Embedded Controller development, Type-C/USB4, and power/boot optimizations. He has driven cross-stakeholder projects delivering DisplayPort 2.1 and USB4 support, migrated Chrome EC to Zephyr for Meteor Lake platforms, and contributed significant low-level fixes to coreboot for Intel platforms. Comfortable across C, C++, Python and tooling languages, he blends machine-learning–era training with deep firmware and SMM expertise. Based in Hillsboro, Oregon, he pairs production-focused engineering with open-source contributions to coreboot that enabled USB and device-tree improvements for Tiger Lake and related boards.
code10 years of coding experience
job7 years of employment as a software developer
bookUniversity of California, San Diego
github-logo-circle

Github Skills (9)

c1710
firmware10
bios10
embedded10
c1110
sys10
boot10
device-tree9
usb9

Programming languages (1)

C

Github contributions (4)

github-logo-circle
coreboot/coreboot

Oct 2015 - Aug 2021

Read-only mirror of https://review.coreboot.org/coreboot.git. Synced every hour. We don't handle Pull Requests.
Role in this project:
userEmbedded Systems Engineer / IoT Developer
Contributions:55 commits in 5 years 10 months
Contributions summary:Brandon primarily contributed to the coreboot project by modifying header files and source code related to Intel's FSP (Firmware Support Package) for the apollolake platform. They updated USB tuning parameters and cleaned up unused parameters within UPD headers. Additionally, the user added and modified code for System Management Mode (SMM) functionality, adding common code for Intel platforms and handling various SMI events. Furthermore, they updated devicetree and configuration files to enable or configure various Tiger Lake and Volteer board features, including USB4/TBT and Type-C port configuration.
corebootfirmwarereviewpull-requestsbootloader
coreboot/chrome-ec

Mar 2022 - Jun 2022

Contributions:23 commits in 3 months
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.
Request Free Trial
Brandon Breitenstein - Software Firmware Engineer at Intel Corporation