Brandon Fry
Senior ASIC Design Engineer at NVIDIA
Portland, Oregon Metropolitan Area United States
Summary
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Senior🎓
Top SchoolBrandon Fry is a Senior ASIC Design Engineer in the Portland area with a decade of hands-on experience architecting high-performance digital systems across FPGA and ASIC domains. He has driven FPGA-to-ASIC transitions at NVIDIA after designing FPGA-based ML accelerators for Azure at Microsoft, and brings deep expertise in Verilog/SystemVerilog/VHDL, timing closure, multi-clock domains, and high-speed interfaces such as JESD204B. His background spans DSP, analog/RF, firmware and software (C/C++)—notably delivering a 30x video refresh improvement for an F-35 helmet display tester and leading a patented DAC synchronization effort in high-speed AWG hardware. A pragmatic team player and problem-solver, he combines system-level architecture with low-level implementation chops and formal training in data science to inform measurement-driven design decisions.
10 years of coding experience
12 years of employment as a software developer
Hardware DSP: A guide to building DSP Circuits in FPGAs, Hardware DSP: A guide to building DSP Circuits in FPGAs at Besser AssociatesVerilog/System Verilog for Design and Synthesis, Verilog/System Verilog for Design and Synthesis at Sutherland HDLBachelor of Science (BS) Electrical and Electronics Engineering, Bachelor of Science (BS) Electrical and Electronics Engineering at Oregon State UniversityMaster of Science - MS Data Science, Master of Science - MS Data Science at University of Colorado BoulderGithub contributions (5)
irfrenchfry01/Project-Codename
Nov 2016 - Nov 2017
Contributions:41 commits, 32 pushes, 2 branches in 1 year
irfrenchfry01/hello-world
Sep 2015 - Sep 2015
Contributions:2 PRs, 2 pushes, 3 branches in 1 day
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