Bronson Edralin
Principal Analog IC Design Engineer at Raytheon Technologies
Greater Phoenix Area United States
Summary
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Senior🎓
Top SchoolBronson Edralin is a Principal Analog IC Design Engineer with 11 years of experience designing high-performance mixed-signal and RF ASICs across CMOS nodes from 250nm to 12/14nm FinFET and specialized processes like SOI and high-voltage. He leads analog design and tapeout activities at Raytheon Technologies, bringing proven delivery on high-speed converters (1–40 GS/s), 10 GHz PLLs/VCOs, SERDES, and complex mixed-signal systems used in aerospace and particle-detection applications. His background blends hands-on Cadence Virtuoso layout/schematic work, foundry interfacing, and test automation software he developed for ASIC production and detector readouts. Notably, he drove his startup’s first multi-GSa/s waveform-sampling SoC tapeouts and automated hardware test stacks using XML-RPC and PostgreSQL integrations. Based in the Greater Phoenix Area, he combines deep circuit-level expertise with practical system integration and manufacturing experience.
11 years of coding experience
8 years of employment as a software developer
Master of Science (M.S.), Master of Science (M.S.) at University of Hawaii at Manoa
Github Skills (1)
electrical-engineering3
Github contributions (4)
bedralin/IDLab_Inventory
Jul 2014 - Jul 2014
Contributions:27 commits in 1 day
bedralin/eesab-website
Feb 2015 - Feb 2015
Contributions:2 pushes in 6 days
electricalengineeringelectrical-engineeringadvisoryboard
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