Can Ma is an experienced ASIC design engineer based in San Jose with nine years focused on digital integration, low-power flows, timing closure and DFT across top-tier companies including Meta, Samsung, Google, Marvell and Amazon Kuiper. He has end-to-end tapeout experience and a proven track record of building hierarchical, highly correlated power and formality flows that sign off production chips and resolve complex ECO and tool issues. His work spans CPF/UPF low-power methodologies, full-chip and custom-layout timing analysis, SpyGlass lint/CDC/RDC automation, and MBIST/DFT flow development for GPU and AI silicon. At Amazon Kuiper he advanced early-stage RTLA power analysis and single-digital correlation with PD, and at Facebook he delivered zero-error CDC hierarchies on billion-gate designs. He also contributes machine-learning tooling on GitHub, integrating BERT fine-tuning into an NER pipeline, showing a breadth beyond hardware into software-driven ML deployment.
Tensorflow solution of NER task Using BiLSTM-CRF model with Google BERT Fine-tuning And private Server services
Role in this project:
ML Engineer
Contributions:44 commits, 7 PRs, 59 pushes in 1 year 2 months
Contributions summary:Ma primarily contributed to the implementation and refinement of a Named Entity Recognition (NER) system using a BiLSTM-CRF model. The commits show modifications to the core NER model, including the addition of training parameters and adjustments to the CRF layer. Furthermore, the user integrated BERT fine-tuning and incorporated server-side support for model deployment and inference, evidenced by the addition of server and client support along with relevant code changes.
Contributions:7 commits, 90 pushes, 1 branch in 1 month
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