Canberk Topal
Senior Design Engineer at Arm
Cambridge, England, United Kingdom
Summary
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Rockstar🎓
Top SchoolCanberk Topal is a Senior Design Engineer based in Cambridge with four years of hands-on experience in digital and embedded hardware design, verification, and FPGA implementation. He has contributed to high-profile open-source silicon projects like lowRISC’s Ibex and OpenTitan—adding FPGA RAM topologies, power-analysis tooling, coverage hooks, ISA decoder fixes, and memory-integrity checks—bridging backend, embedded, and automation workstreams. At Riverlane he designed low-microsecond quantum error-correction hardware and shipped leakage-aware decoders used in published experiments, and he now brings that low-latency hardware mindset to Arm. Comfortable across RTL, verification, and system integration, he’s as likely to write a UVM testbench or synthesis constraints as to prototype on an Arty A7 board. A detail-oriented engineer who enjoys “chips” in both senses, he combines practical FPGA/SoC delivery with published research-driven innovation.
4 years of coding experience
4 years of employment as a software developer
Bachelor of Science - BS Electrical Electronics and Communications Engineering, Bachelor of Science - BS Electrical Electronics and Communications Engineering at Istanbul Technical University
English, Turkish
Stackoverflow
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Github Skills (22)
verilog10
systemverilog10
architecture10
computer-architecture10
risc-v10
hardware10
vhdl10
digital-design10
sys10
instruction-set10
fpga10
hdl10
embedded10
architectures10
xilinx9
Programming languages (4)
Github contributions (5)
lowRISC/ibex
Jul 2021 - Jan 2023
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Role in this project:
Embedded Systems Engineer / Automation Engineer
Embedded Systems Engineer / Automation EngineerContributions:127 reviews, 67 commits, 68 PRs in 1 year 6 months
Contributions summary:Canberk primarily contributed to the FPGA implementation of the Ibex RISC-V CPU core. Their work involved modifying the core's top-level design to use 2-port RAM for instruction and data storage. They added scripts for power analysis in the Arty A7 FPGA example and incorporated coverage support using Cadence tools. Furthermore, they integrated scrambling RAM primitives into the ICache, updated parameters for OpenTitan builds, and implemented memory integrity error checks.
risc-vcpuzeroibex32-bit
lowRISC/opentitan
Aug 2021 - Jan 2023
OpenTitan: Open source silicon root of trust
Role in this project:Back-end & Embedded Systems Engineer
Back-end & Embedded Systems EngineerContributions:290 reviews, 142 commits, 144 PRs in 1 year 5 months
Contributions summary:Canberk primarily contributed to the OpenTitan project by fixing bugs and implementing enhancements related to the OTBN (OpenTitan's custom processor) core, particularly the instruction set architecture (ISA) decoder and memory operations. The user addressed issues in decoding SRLI/SLLI instructions, implemented a snippet generator for known WDR (Write Data Register) values, and added coverage points for detecting out-of-bounds memory addresses in load/store instructions. Furthermore, they worked on model-related bug fixes and implemented functionalities for handling the EDN (Entropy Device Network) interface and RMA (Return Merchandise Authorization) requests.
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