Candace Philip is a senior silicon design engineer with 12 years of experience and a PhD in Computer Engineering from the University of Maryland, currently shaping next-generation Zen CPU cores at AMD. Her doctoral research explored monolithic integration of non-volatile memory with CPUs—especially over last-level caches—giving her rare cross-cutting expertise in microarchitecture and emerging memory technologies. She has practical FPGA and reliability experience from NASA projects and has taught and developed lab curricula, reflecting strong mentorship and engineering-education skills. Based in Boxborough, MA, Candace blends deep research pedigree with hands-on silicon delivery, uniquely positioning her to drive architectural innovation that bridges academic ideas and production CPU design.
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Candace Philip - MTS Silicon Design Engineer at AMD