Summary
Cayetano Santos is a Senior VHDL Design Engineer with over 15 years delivering high-performance firmware and data acquisition systems for international physics research and industry projects. He blends deep expertise in FPGA/VHDL design, algorithm development, and system integration with hands-on experience across experiments like JUNO and DUNE. Having led electronics departments and multi-national teams, he couples technical leadership and budget/project management with a pragmatic, creative approach to problem solving. His background spans real-time image and signal processing, high-throughput DAQ architectures (1 GHz, 12-bit systems, DDR memory interfaces) and firmware-to-software toolchains including Matlab-based control. Trilingual and accustomed to cross-border collaborations, he thrives in focused, high-expertise teams and is actively open to new international FPGA/VHDL opportunities. An engineer who prefers building reliable, hardware-accelerated solutions, he often reduces data complexity in-stream to deliver measurable system-level gains.
11 years of coding experience
Master in Computer Science and Telecommunication Engineering, Embedded Electronics, Master in Computer Science and Telecommunication Engineering, Embedded Electronics at Universidad Autónoma de Madrid
Summer school, Programmable logic devices and digital architectures, Summer school, Programmable logic devices and digital architectures at Universidad de Alcalá
5-year Master’s Degree, Physical Sciences, 5-year Master’s Degree, Physical Sciences at Universidad Complutense de Madrid
Italian, English, Spanish, French