César Fuguet
Researcher In Computer Architecture at Polytech Grenoble
Grenoble, Auvergne-Rhône-Alpes, France
Summary
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Rockstar🎓
Top SchoolCésar Fuguet is a researcher and hardware-focused computer architect with nine years of experience designing multicore processors, accelerators and reliable cache subsystems for RISC-V and FPGA targets. Based in Grenoble, he combines academic rigour—as a PhD holder and university lecturer at Polytech Grenoble—with hands-on R&D at CEA and contributions to major open-source projects like the CORE-V CVA6, where he optimized data cache configuration and AMO handling. His work in the European Processor Initiative reflects a track record of translating research into deployable processor technology for scientific computing. Known for bridging SystemC/VHDL prototyping with production-oriented processor design, he brings deep expertise in fault tolerance, memory coherence and accelerator integration.
10 years of coding experience
12 years of employment as a software developer
5 year System Engineer, 5 year System Engineer at Universidad de los Andes (VE)Doctor of Philosophy (Ph.D.) Computer Science, Doctor of Philosophy (Ph.D.) Computer Science at Pierre and Marie Curie University
Spanish, English, French
Github Skills (5)
cpu10
risc-v10
systemverilog-hdl10
asic9
fpga9
Programming languages (7)
Github contributions (5)
openhwgroup/cva6
Mar 2023 - Apr 2026
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
Role in this project:
Embedded Systems Engineer
Embedded Systems EngineerContributions:33 reviews, 47 PRs, 2 pushes in 3 years 2 months
Contributions summary:César primarily contributed to the definition and configuration of the CVA6 processor's cache subsystem, specifically the data cache (Dcache). They made several changes related to cache size definitions, memory transaction ID width, and the addition of the HPDcache. Furthermore, the user addressed the correct handling of AMO (Atomic Memory Operations) instructions. These changes indicate a focus on optimizing and adapting the cache subsystem for the target RISC-V processor, including configuration for the FPGA.
linuxrisc-vsystemverilog-hdlcpuasic
openhwgroup/cv-hpdcache
Feb 2023 - Feb 2023
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
Contributions:3 releases, 26 reviews, 1 commit in 1 day
dcache
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