Cesare Garlati
Sailing Yacht Master at The High Seas
San Francisco, California, United States
Summary
👤
Senior🎓
Top SchoolCesare Garlati is a security-focused founder and technologist with nine years of concentrated experience building embedded systems and IoT security, most recently as Co-Founder & CEO of Hex Five Security. Based in San Francisco, he blends deep technical roots (MS EECS) with business leadership (MBA, UC Berkeley) and a history of strategic roles from VP Mobile Security to Chief Security Strategist. He has steered industry working groups and product teams at organizations like the Cloud Security Alliance, prpl Foundation, and Trend Micro, shaping mobile and embedded security standards. Cesare pairs entrepreneurial grit with hands-on engineering, often applying practical security architectures to high-tech hardware—now maintained at sea as a Sailing Yacht Master protecting his investments. An active promoter of embedded security, he publishes work and updates through hex-five.com, demonstrating a rare combination of operational seamanship and cyber defense expertise.
9 years of coding experience
23 years of employment as a software developer
Master of Business Administration (M.B.A.), Master of Business Administration (M.B.A.) at University of California, BerkeleyMaster of Science - MS EECS - Electrical Engineering and Computer Sciences, Master of Science - MS EECS - Electrical Engineering and Computer Sciences at Politecnico di Milano
English, Italian
Stackoverflow
1reputation
0reached
0answers
0questions
Github Skills (47)
ieee10
risc10
simulator9
risc-v9
security9
tee9
spike9
computer-architecture8
esp326
eclipse-marketplace6
validity5
eclipse5
interrupt5
plug5
ssa4
Programming languages (3)
Github contributions (5)
hex-five/multizone-sdk-andes
Sep 2021 - Aug 2023
Contributions:3 releases, 12 pushes, 3 branches in 1 year 11 months
hex-five/multizone-sdk
Dec 2018 - Jan 2023
MultiZone® Security TEE for RISC-V
Contributions:14 releases, 236 commits, 4 PRs in 4 years 1 month
risc-vteeriscvsecurityrisc
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