Senior Signal Integrity Solutions Architect at NVIDIA
Seattle, Washington, United States
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Summary
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Charles Clayton is a Senior Signal Integrity Solutions Architect with 11 years of experience designing and debugging high-speed PHYs, transceivers, and networking IP across FPGA and ASIC platforms. Currently at NVIDIA after senior FAE roles at Intel/Altera, he combines deep RTL background with practical board bring-up, timing closure, and transceiver troubleshooting for telecommunications, medical, and AI customers. An automation and scripting enthusiast, he regularly builds Bash/TCL/Python tooling and data-visualization aids to speed development and simplify complex debug workflows. He has led HSIO-focused FAE groups, stepped into regional transceiver specialist roles, and completed advanced SI coursework to formalize his expertise. Comfortable across Quartus and Vivado toolchains, Charles also brings experience shipping demo systems (400G Ethernet) and producing instructional content, reflecting a blend of technical depth and clear communication. Based in Seattle, he’s a Linux user who enjoys turning verbose HDL and messy measurement data into actionable, repeatable solutions.
11 years of coding experience
10 years of employment as a software developer
Italian Language Immersion Level 1 and 2, Italian Studies, Italian Language Immersion Level 1 and 2, Italian Studies at Seattle Central College
Bachelor of Applied Science, Electrical Engineering, Bachelor of Applied Science, Electrical Engineering at The University of British Columbia
Contributions:42 commits, 43 pushes, 1 branch in 8 months
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Charles Clayton - Senior Signal Integrity Solutions Architect at NVIDIA