Summary
Charlotte Reed is a seasoned senior engineer with over 30 years of experience in logic design and functional verification, currently leading a memory controller verification team for IBM server platforms. She has deep expertise in DDR3/DDR4 memory calibrations, refresh protocols, high-speed serial interfaces, and processor core verification dating back to PowerPC designs for Apple, Nintendo, and IBM. A reliable team leader and hands-on coder, she has guided multi-core and PHY verification efforts and built C-based pseudo-random verification environments for embedded video and cache systems. Her career spans mainframe modules through modern server ASICs, giving her a rare end-to-end view of silicon design, verification, and system-level integration. Based in Underhill, Vermont, she pairs rigorous technical discipline (MS in Computer Engineering, Syracuse University) with a practical focus on regression, debug, and shipping high-quality designs. Colleagues note her loyalty and steady leadership across long, complex product cycles—often driving the verification strategies that make mission-critical systems reliable.
5 years of coding experience
Masters of Science, Computer Engineering, 3.7, Masters of Science, Computer Engineering, 3.7 at Syracuse University