Chen Qian
DPU Logic Designer at ByteDance
Pudong, Shanghai, China
Summary
👤
Senior🎓
Top SchoolChen Qian is a DPU logic designer with nine years of experience designing and verifying large-scale ASICs and FPGAs for CPU, GPU and domain-specific accelerators. Currently at ByteDance, he architected and developed the company's in-house DPU cards, bringing system-level FPGA/ASIC expertise to production accelerator hardware. Previously at IBM he led OpenCAPI/CAPI enablement and POWER9 verification work, including formal verification and end-to-end UVM environments for memory and accelerator interfaces. His background spans heterogeneous acceleration, board support integration and performance testing, giving him a rare blend of low-level hardware design and system integration skills. A Ph.D. student at Shanghai Jiao Tong University researching deep learning with fluid simulation, he pairs cutting-edge academic work with practical chip development. Based in Pudong, Shanghai, he’s comfortable translating research ideas into silicon and FPGA prototypes for real-world workloads.
9 years of coding experience
4 years of employment as a software developer
High School Diploma, High School/Secondary Diplomas and Certificates, High School Diploma, High School/Secondary Diplomas and Certificates at High School Affiliated to Nanjing Normal UniversityBachelor of Engineering (B.E.), Integrated Circuits Design, Bachelor of Engineering (B.E.), Integrated Circuits Design at Shanghai Jiao Tong University
Github Skills (16)
pde-solver9
3d-reconstruction7
computer-vision6
function-approximation6
transparency6
deep-learning6
computer-graphics6
pde6
realtime5
machine-learning5
cuda5
lightning4
automatic-differentiation4
neural-network3
gpu3
Programming languages (2)
Github contributions (5)
cathyxl/Project-Consumer-Groups
Mar 2018 - Apr 2018
Contributions:10 commits, 9 pushes in 28 days
hehehaha12138/terrorismResearch
Mar 2018 - Mar 2018
Contributions:6 commits, 5 pushes in 4 days
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