Chenxiao Zhu
UArch And RTL Design Engineer at Rivos Inc.
California, United States
Summary
👤
Senior🎓
Top SchoolChenxiao Zhu is a Silicon Engineer with nine years of hands-on experience in ASIC design and verification, currently based in California and working across Meta and Rivos on microarchitecture and RTL. Trained at Cornell (M.Eng. in Computer Hardware Engineering) and UW–Madison (B.S. ECE), Chenxiao built early verification expertise at NVIDIA and Qualcomm, contributing UVM-based testbenches and coverage-driven validation for complex multi-GPU and SoC designs. Adept at bridging uArch intent with RTL implementation, they focus on scalable verification infrastructure and measurable coverage closure. Chenxiao’s career shows a steady progression from intern to cross-company contributor, with a practical knack for turning architectural requirements into verifiable RTL. Colleagues describe them as detail-oriented yet pragmatic, often surfacing subtle corner-case behaviors that improve silicon resilience. They are actively pursuing opportunities to lead verification efforts that push performance and reliability boundaries in advanced silicon.
9 years of coding experience
3 years of employment as a software developer
Bachelor's degree Electrical and Computer Engineering, Bachelor's degree Electrical and Computer Engineering at University of Wisconsin-MadisonMaster of Engineering Computer Hardware Engineering, Master of Engineering Computer Hardware Engineering at Cornell UniversityGithub contributions (5)
Shawnzhu2051/TextClassifierByPytorch
Jun 2018 - Jul 2018
Contributions:8 commits, 7 pushes in 16 days
Shawnzhu2051/Shawnzhu2051.github.io
Apr 2017 - Nov 2018
Contributions:75 pushes, 1 branch in 1 year 6 months
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