Chien Lan - Senior Software Engineer, Artificial Intelligence Group at AMD

Chien Lan

Senior Software Engineer, Artificial Intelligence Group at AMD

California, United States

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Summary

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Senior

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Top School

Chien Lan is a Senior Software Engineer in AMD’s Artificial Intelligence Group with eight years of hands-on experience bringing generative AI to edge hardware through runtime, inference, and deployment engineering. He has deep expertise in FPGA/AI accelerator stacks, having built high-performance runtime schedulers, PCIe/kernel drivers, and virtualization features at Xilinx that enabled million-IOPS scheduling and >99% host memory traffic savings. Comfortable across C/C++, Python, OpenCL and Linux kernel internals, he bridges low-level driver design and system-level memory/DMA management to optimize inference on constrained devices. An active contributor to Xilinx’s XRT runtime, he’s proven at turning complex hardware interfaces into stable, production-ready software for cloud and edge platforms. Based in California, he combines academic rigor from top engineering programs with a pragmatic record of shipping optimized, scalable acceleration stacks.

7 years of coding experience

7 years of employment as a software developer

Bachelor's degree, Electrical and Electronics Engineering, Bachelor's degree, Electrical and Electronics Engineering at National Chiao Tung University

San José State University

Master's degree, Electrical, Electronics and Communications Engineering, 3.93, Master's degree, Electrical, Electronics and Communications Engineering, 3.93 at National Taiwan University

English, Chinese, Japanese

Stackoverflow

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Github Skills (7)

fpga10

memory-management10

c-language10

device-driver10

driver10

api10

cprogramming-language10

Programming languages (2)

C++C

Github contributions (5)

Xilinx/XRT

Jun 2018 - Sep 2022

Run Time for AIE and FPGA based platforms

Role in this project:

Back-end Developer

Contributions:90 reviews, 468 commits, 459 PRs in 4 years 4 months

Contributions summary:Chien primarily contributed to the driver runtime (XRT) of the Xilinx FPGA platform, focusing on implementing and describing functionality related to the Write Buffer Object (BO) and copy operation. The commits involved adding information, describing function, support for counter reset and adding support for the creation of a board and the memory configuration with a focus on the use of API IOCTLs. These changes demonstrate the user's understanding of driver development and its integration with memory management within the Xilinx platform.

vitisxilinxlinux-kernelxrtfpga

chienwei-lan/XRT

Oct 2018 - Mar 2023

Contributions:12 PRs, 6841 pushes, 718 branches in 4 years 5 months

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