Chin Ang
Senior Manager at Lattice Semiconductor
Penang, Malaysia
Summary
👤
Senior🎓
Top SchoolChin Ang is a senior engineering leader with nine years of recent experience and a deep hands-on background in FPGA and SoC platforms, currently leading engineering efforts at Lattice Semiconductor from Penang, Malaysia. He has a strong track record building and managing ~20-person teams focused on soft-IP, system integration tooling, embedded processor verification, RTOS/firmware, and FPGA debug infrastructure. Chin’s career at Altera and Intel includes shipping multiple Nios V soft-CPU variants, prototyping on-chip debug subsystems, and driving Platform Designer enhancements such as AXI modelling and board-aware flows. Equally comfortable in firmware, Linux/Yocto integration, and RTL/IP work, he combines low-level technical craftsmanship with stakeholder-aligned roadmap delivery. Notably, his profile reflects a rare blend of product-facing management and continuing hands-on FPGA debug/design entry expertise, evidenced by active GitHub ties to FPGA design entry and debug.
9 years of coding experience
18 years of employment as a software developer
Bachelor of Engineering (B.Eng.), Mechatronics, Robotics, and Automation Engineering, Bachelor of Engineering (B.Eng.), Mechatronics, Robotics, and Automation Engineering at Universiti Teknologi MalaysiaO Level, Science, O Level, Science at S.M.J.K. Jit Sin
Japanese, Chinese, English, Malay
Github Skills (48)
eclipse-ide10
integrate9
ide-plugin9
openembedded9
eclipse8
git-repository8
yocto8
structures7
java7
hypervisor7
eclipse-cdt7
yocto-project7
eagle7
acpi6
qbcore-framework6
Programming languages (5)
Github contributions (5)
crops/eclipse-crops
Aug 2017 - Nov 2017
Contributions:23 commits, 7 pushes, 3 branches in 3 months
javaeclipse-plugineclipsecrops
ChinHuatAng/eclipse-yocto
Feb 2018 - Nov 2018
Contributions:57 pushes, 15 branches in 8 months
yocto-projecteclipse-ideideeclipseembedded
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