FPGA-based TJDS SMVP accelerator implemented in Verilog.
Contributions:2 releases, 23 commits, 7 PRs in 6 days
fpgaverilog
Implement sparse matrix vector product calculations using CSR and TJDS compression algorithms. This program is part of university coursework.
Contributions:3 releases, 10 PRs, 54 pushes in 2 months
compression-algorithmsparse-matrix