Ciro Ceissler
Senior Digital Verification Engineer
Munich, Bavaria, Germany
Summary
👤
Senior🎓
Top SchoolCiro Ceissler is a Senior Digital Verification Engineer with 12 years of experience applying pre-silicon verification and software techniques to boost productivity, performance and maintainability in semiconductor projects. Currently at NXP in Munich after senior roles at Renesas and Dialog, he combines deep SystemVerilog/UVM expertise with model-based, formal and DPI-driven verification approaches honed on automotive safety-critical sensors, PMICs and high-speed ASICs. He has a strong research background (Master’s in Computer Science) and prior FPGA/automation work at Microsoft building frameworks that connect SystemVerilog and Python, reflecting his focus on developer-friendly verification infrastructure. Comfortable across low-level embedded firmware to top-level SoC verification, he also brings hands-on automation and tooling experience (Python, scripting, coverage analysis, formal flows) that shortens tape-out cycles. Notably, his career blends industrial delivery with academic research, enabling pragmatic adoption of advanced methods like formal verification and model-based testing in production flows.
11 years of coding experience
16 years of employment as a software developer
Graduate Computer Engineer, Graduate Computer Engineer at Universidade Federal de PernambucoMaster’s Degree Computer Science, Master’s Degree Computer Science at Universidade Estadual de Campinas
English
Stackoverflow
1reputation
0reached
0answers
0questions
Github Skills (3)
openmp1
clang1
cpp1
Github contributions (5)
LSC-OpenMP/clang
May 2017 - Sep 2019
Contributions:2 PRs, 19 pushes, 4 branches in 2 years 4 months
omphardcloud/hardcloud
Oct 2017 - Feb 2020
Contributions:161 commits, 88 pushes, 10 branches in 2 years 4 months
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