Colin Schmidt
Senior Staff Engineer at SiFive
Mountain View, California, United States
Summary
🤩
Rockstar🎓
Top SchoolColin Schmidt is a Senior Staff Engineer in Mountain View with 12 years of experience building and hardening RISC-V systems, tooling, and simulation infrastructure. At SiFive and during a long PhD at UC Berkeley he focused on end-to-end SoC development—from data-parallel vector architectures in silicon to the software stacks that program them. He is a hands-on backend and infrastructure engineer with deep open-source impact on flagship projects in the RISC-V ecosystem (Chisel, Rocket Chip, Chipyard, and FIRRTL), contributing fixes, build automation, and memory/annotation refactors that improve compiler and simulation reliability. His kernel work added rich syscall and mmap support to the RISC-V proxy kernel, showing comfort at the boundary between hardware and low-level OS software. Known for improving developer workflows—verbose simulation logging, hex-generation for fast loads, and gate-level integration—he combines research rigor with production-grade engineering.
12 years of coding experience
9 years of employment as a software developer
Doctor of Philosophy (Ph.D.) Computer Science, Doctor of Philosophy (Ph.D.) Computer Science at University of California, BerkeleyBS Computer Science & Computer Engineering, BS Computer Science & Computer Engineering at Cornell University
Github Skills (34)
simulation10
verilog10
filesystem10
gnu-make10
simulations10
risc-v10
memory-management10
firrtl10
c1110
makefile10
intermediate-code10
scala10
c1710
system-calls10
compiler-design10
Programming languages (8)
Github contributions (5)
ucb-bar/chipyard
Apr 2017 - Apr 2021
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Role in this project:
Backend & DevOps Engineer
Backend & DevOps EngineerContributions:79 reviews, 89 commits, 63 PRs in 4 years
Contributions summary:Colin primarily contributes to the build system and simulation infrastructure of the Chipyard framework. They added features to improve simulation, such as verbose logging and the ability to generate hex files for faster loading. They also made modifications to build scripts (common.mk and variables.mk) and documentation (docs/VLSI/HAMMER.rst), indicating a focus on build automation, simulation workflow, and documentation. Furthermore, they worked on integrating gate-level simulation capabilities through changes to the vcs.mk file.
rtlout-of-orderhardware-designsvlsicomputer-engineering
chipsalliance/rocket-chip
Mar 2015 - Aug 2020
Rocket Chip Generator
Role in this project:Backend Developer
Backend DeveloperContributions:255 commits, 62 PRs, 196 pushes in 5 years 5 months
Contributions summary:Colin primarily contributed to the `rocket-chip` project by fixing bugs within the core functionality. Their work involved addressing issues related to bitwidth and decoding logic within the `decode.scala` file. They also made additions to the rocc interface by adding an fpu port. The user's commits demonstrate a focus on improving the stability and functionality of the hardware design within this RISC-V chip generator project.
rtlriscvchipchiselscala
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