Conor O'reilly
Director Software Engineering at Optum
Greater Dublin Ireland
Summary
👤
Senior🎓
Top SchoolConor O'Reilly is a seasoned technology leader and product director with over 25 years of international experience and more than a decade in senior roles, currently leading Clinical Solutions, Risk Adjustment, Analytics & AI at Optum. He combines deep data and software engineering expertise with product and program management to build and reengineer teams, platforms and operational analytics pipelines—often bringing research-led innovation into production. His background spans cloud-based near-realtime clinical data platforms, large-scale log ingestion for security analytics, and NLP-driven regulatory and safety products, reflecting a rare mix of healthcare, security and enterprise data experience. A committed educator, he has lectured at multiple Irish universities for seven-plus years and holds three patents, signalling both practical and inventive impact. He also contributes to open-source hardware tooling, having enhanced the Verilog-to-Routing CAD flow to better handle initial latch values and simulation integrity, showing an ongoing hands-on engineering curiosity beyond executive responsibilities.
13 years of coding experience
28 years of employment as a software developer
MSc Technology and Learning, MSc Technology and Learning at Trinity College DublinBSc. Computer Science, BSc. Computer Science at Griffith College DublinCertificate in Visual Arts Practice (Level 7), Certificate in Visual Arts Practice (Level 7) at National College of Art & DesignColaiste Eanna, BallyroanBSc. Applied Physics, BSc. Applied Physics at Dublin City UniversityAnalyst Programmer (CP6) Course, Analyst Programmer (CP6) Course at Nixdorf Centre for Advanced Technology Training
Github Skills (8)
c1710
synthesis10
verilog10
c1110
eda10
cad9
fpga9
url-routing9
Programming languages (1)
Github contributions (5)
verilog-to-routing/vtr-verilog-to-routing
May 2013 - Dec 2013
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Role in this project:
Back-end Developer
Back-end DeveloperContributions:20 commits in 7 months
Contributions summary:Conor focused on enhancing the Verilog-to-Routing (VTR) flow by adding support for initial latch values within the netlist creation process. Their contributions involved modifying the code to correctly handle and propagate initial values for registers and wires. The changes included updates to the ODIN_II code base, specifically impacting the generation of BLIF files and the handling of simulation values. Furthermore, they addressed compatibility issues in benchmark Verilog files and fixed memory address boundary checking for simulation.
vtrcadedaplacementsynthesis
crmymh/verilator
Jun 2020 - Jun 2020
Verilator open-source SystemVerilog simulator and lint system
Contributions:2 pushes, 1 branch in 1 day
simulatorsystemveriloglintverilator
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