Cristobal Ramirez
Sr. Staff Design Engineer - Microarchitect at MIPS
Austin, Texas, United States
Summary
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Senior🎓
Top SchoolCristobal Ramirez is a Sr. Staff Design Engineer and microarchitect with eight years specializing in high-performance scalar and vector CPU design, currently contributing to MIPS after leading vector core development at SiFive. He has deep hands-on experience defining microarchitecture, RTL implementation, synthesis, timing closure, and RTL power reduction for out-of-order superscalar and very-long-vector designs. His work spans industry and research—driving RISC-V vector VPU and superscalar core projects at Barcelona Supercomputing Center and designing Lagarto cores from concept to pipeline implementation. Comfortable across simulation (gem5), timing analysis, and RTL-level optimization, he blends academic rigor (PhD-level computer architecture training) with production-grade core IP delivery. Notably, he has evaluated vector configurations up to 16k-bit lengths and led full-pipeline implementations, a niche expertise that bridges next-generation accelerator research and commercial silicon.
8 years of coding experience
6 years of employment as a software developer
The National Polytechnic Institute of MexicoUPC Universitat Politècnica de CatalunyaNational Technical University of AthensBachelor's degree, Mechatronics Engineering, Bachelor's degree, Mechatronics Engineering at Universidad Tecnológica de la Mixteca
Github Skills (12)
vectorization9
risc-v9
simd9
spike8
upstream8
simulator8
gem57
simulation7
synchronized7
risc7
computer-architecture6
benchmark2
Programming languages (2)
Github contributions (5)
RALC88/gem5
Jun 2020 - Aug 2021
This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.
Contributions:83 commits, 2 PRs, 98 pushes in 1 year 2 months
storedsynchronizedsimulationreviewupstream
RALC88/mcpat
Jul 2021 - Jul 2021
An integrated power, area, and timing modeling framework for multicore and manycore architectures
Contributions:16 pushes in 18 days
architecturesintegratedmulticoremanycorepower
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