Cuong Le

Principal Design Verification Engineer

San Jose, California, United States
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Summary

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Senior
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Top School
Cuong Le is a Principal Design Verification Engineer based in San Jose with 10 years of hands-on experience verifying complex SoC and security IP using UVM/SystemVerilog and UVM/SystemC. He has progressed through senior verification roles at Marvell and Qualcomm, owning verification environments for NVMe, RDMA, AMBA interconnects and advanced security blocks like pIMEM and TME on Snapdragon platforms. His background in embedded Linux, bootloaders, device drivers and automotive protocols (CAN, KW2000) gives him rare full-stack insight from firmware to RTL, which he leverages when debugging cross-domain issues and integrating IP into full-chip flows. He contributed to the Accellera effort to standardize UVM-SystemC, reflecting his interest in tooling and verification methodology beyond day-to-day projects. Known for remote collaboration with international teams (notably Marvell Israel) and coordinating SoC-level verification across IP domains, he combines deep technical craft with practical delivery. Trained in computer engineering with an honors degree, he brings both protocol-level rigor and system-level pragmatism to high-assurance silicon projects.
code10 years of coding experience
job11 years of employment as a software developer
bookMathematics, Mathematics at Luong Van Chanh high school for the gifted
bookHonor Bachelor's degree Computer Engineering, Honor Bachelor's degree Computer Engineering at Ho Chi Minh City University of Technology
languagesEnglish, Vietnamese
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Github Skills (7)

alu10
methodology6
uvm5
verification5
co-simulation3
qemu2
systemc1

Programming languages (1)

C++

Github contributions (5)

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This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit
Contributions:19 commits in 19 days
universal-verification-methodologyunitmethodologyaluverification
hcuongvn/simple-alu-uvm

Jul 2018 - Jun 2019

Contributions:16 pushes, 1 branch in 11 months
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Cuong Le - Principal Design Verification Engineer