Summary
Daksh Dharod is a Sr. DFT Engineer with nine years of hands-on experience driving testability, scan ATPG, and advanced fault modeling for complex SoCs across Intel, AMD, and NVIDIA. He combines deep silicon-failure analysis skills—photo-emission, LVP, lock-in thermography and X‑ray—with practical pattern bring-up and yield improvement strategies to reduce test time and boost coverage. At Intel he pioneered isolation techniques for internal I/O defects in stacked-die packages, and at AMD he bridged RTL and physical design to harden next‑gen designs for production. Now at NVIDIA, he focuses on scaling DFT approaches for high-performance SoCs while maintaining a strong bias for root-cause debug. Colleagues value his blend of lab-proven failure analysis and pragmatic ATPG engineering that translates directly into higher silicon yield.
9 years of coding experience
8 years of employment as a software developer
Master's degree Electrical and Electronics Engineering, Master's degree Electrical and Electronics Engineering at Portland State University
High School Computer Science, High School Computer Science at Shri T.P Bhatia Junior College of Science
Bachelor's degree Electrical and Electronics Engineering, Bachelor's degree Electrical and Electronics Engineering at Dj sanghvi college of engineering
Marathi, Gujarati, Hindi, English