Damien Pretet
Senior Digital Designer at STMicroelectronics
Aix-en-Provence, Provence-Alpes-Côte d'Azur, France
Summary
👤
Senior🎓
Top SchoolDamien Pretet is an electronics engineer and Senior Digital Designer with over 18 years in the field and a decade focused on FPGA/ASIC design across telecommunications and semiconductor leaders like STMicroelectronics, Rambus and PLDA. He blends deep digital design and DSP foundations with hands-on FPGA implementation and IP development, having moved between individual contributor and management roles including FPGA Design Manager at Accelize. Based in Aix-en-Provence, he excels at translating complex system requirements into efficient silicon- and FPGA-ready architectures, often operating at the intersection of ASIC verification and FPGA prototyping. A pragmatic problem-solver, he brings continuity from early embedded projects through modern SoC design flows, and a track record of adapting quickly across startups and large enterprises.
11 years of coding experience
12 years of employment as a software developer
License of Science Engineering, Electronic Curriculum, License of Science Engineering, Electronic Curriculum at UFR ST - Université de Franche-Comté, BesancçonMaster of Electronic Engineering, Communication & Systems / Digital Signal Processing, Master of Electronic Engineering, Communication & Systems / Digital Signal Processing at UFR ST - Université de Franche Comté, Besancçon
English, French
Github Skills (72)
verilog10
simulator10
testcase10
synthesis10
autocomplete10
language-server-protocol10
timing10
vim-plugin10
asic10
soc10
arm10
binary-tree10
async10
gtkwave10
crossbar10
Programming languages (11)
Github contributions (5)
dpretet/dotfiles
Mar 2017 - Jan 2023
Contributions:216 commits, 302 pushes, 2 branches in 5 years 10 months
dpretet/friscv
Feb 2021 - Dec 2022
RISCV CPU implementation in SystemVerilog
Contributions:9 releases, 151 commits, 472 pushes in 1 year 10 months
risc-vsystemverilogriscv-cpuriscvrv32i
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