Dan Hotoleanu
Field-Programmable Gate Arrays Engineer
Cluj-Napoca, Romania
Summary
🤩
Rockstar🎓
Top SchoolDan Hotoleanu is an FPGA engineer with six years of focused experience designing HDL-based data acquisition systems and demonstrating high-speed ADC/DAC boards at Analog Devices from a strong embedded-software and verification background. He architects Xilinx-based systems combining vendor IP and custom Verilog, implements JESD204B transports, and has hands-on experience with dynamic partial reconfiguration and Linux-integrated test applications. His contributions to Analog Devices’ popular hdl repository include reference designs that integrate AD9656 ADCs with ZCU102 platforms, evidencing practical expertise in bridging FPGA logic, transport layers, and board-level evaluation. Earlier roles across chip validation, automotive FPGA projects, and teaching VHDL give him a rare mix of lab instrumentation, verification scripting, and mentoring experience. Based in Cluj-Napoca, Romania, he pairs academic rigor (Master’s in Computer Science in Engineering) with pragmatic delivery of high-throughput FPGA solutions.
6 years of coding experience
7 years of employment as a software developer
Master's degree, Computer Science in Engineering, Master's degree, Computer Science in Engineering at Technical University of Cluj Napoca
English, French
Github Skills (5)
fpga10
hdl10
verilog10
jes10
xilinx9
Programming languages (3)
Github contributions (5)
analogdevicesinc/hdl
Aug 2020 - Jun 2022
HDL libraries and projects
Role in this project:
Embedded Systems Engineer
Embedded Systems EngineerContributions:34 reviews, 34 commits, 27 PRs in 1 year 10 months
Contributions summary:Dan contributed to the Analog Devices HDL repository by adding and modifying Verilog code, particularly related to the ad9656 and fmcjesdadc1 projects. Their work focused on implementing reference designs for evaluation boards, specifically integrating the AD9656 ADC with a ZCU102 carrier board and updating the JESD204B transport layer instances within the design. These changes involved modifying system-top and block design files, configuring JESD204B parameters, and incorporating new TPL IP modules for data transfer. The user's contributions demonstrate expertise in HDL design for FPGA-based data acquisition systems.
fpgaasicjesd204bhdlvhdl
hotoleanudan/hdl
Feb 2021 - Mar 2022
HDL libraries and projects
Contributions:38 pushes, 8 branches in 1 year 1 month
multicoreodinhdldm
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