Daniel Cederman is a software engineer with 12 years of experience specializing in low-level systems and embedded SPARC platforms, currently based in the Greater Gothenburg area. At Frontgrade Gaisler he works on board support and toolchain integration, drawing on a strong academic foundation from a PhD and postdoc at Chalmers University of Technology. He is an active open-source contributor to projects like GCC and RTEMS, where his patches add LEON5 support, SPARC errata workarounds, instruction-scheduler improvements, and BSP support for controllers such as SMC91111 and GR712RC. His work combines compiler backend changes and real-time OS BSP fixes, showing a rare dual fluency in compiler internals and hardware integration. Colleagues rely on him to improve reliability and performance at the intersection of silicon quirks and toolchain code generation. Outside typical product roles, he brings research-grade rigor to practical embedded engineering problems.
12 years of coding experience
MSc, Computer Science and Engineering, MSc, Computer Science and Engineering at Chalmers University of Technology
Mirror only see https://gitlab.rtems.org/rtems/rtos/rtems
Role in this project:
Embedded Systems Engineer / IoT Developer
Contributions:54 commits in 8 years 9 months
Contributions summary:Daniel primarily contributes to the RTEMS operating system, specifically focusing on BSP (Board Support Package) modifications for various SPARC-based embedded systems. Their contributions include adding support for new hardware, such as the SMC91111 Ethernet controller and GR712RC. They also improve the reliability and performance of the system through code cleanup and bug fixes, like addressing the UT699 and GR712 sleep-mode d-cache issues. These changes demonstrate expertise in low-level system programming and hardware integration.
Contributions summary:Daniel contributed to the GCC compiler, specifically focusing on the SPARC architecture. Their work involved implementing and refining errata workarounds for the SPARC architecture, modifying the instruction scheduler, and adding support for the LEON5 processor. They introduced new predicates for identifying store and load instructions. Additionally, they optimized code generation by skipping empty assembly statements and preventing atomic instructions at the beginning of functions in certain scenarios.
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Daniel Cederman - Software Engineer at Frontgrade Gaisler