Daniel Jepson
Chief Program Manager at NI (National Instruments)
Austin, Texas, United States
Summary
👤
Senior🎓
Top SchoolDaniel Jepson is a pragmatic engineering leader and program manager with nine years of experience delivering mixed-signal and RF products, now serving as Chief Program Manager at National Instruments in Austin. He combines hands-on FPGA and low-level hardware expertise—demonstrated by contributions to EttusResearch's widely used USRP repositories around JESD204B, clocking, and CPLD control—with strategic ownership of multi-million-dollar development portfolios. He’s led global digital engineering teams of 75+, directly managed cross-functional R&D groups, and overseen $20M in programs while driving staffing, skills development, and product sustaining. Equally comfortable in the lab validating synchronization and timing as he is coordinating program delivery, he’s known for improving signal integrity through timing-constraint overhauls and hardware revision support. His background (MEng in Electrical and Electronics Engineering) and blend of deep technical troubleshooting with program-level accountability make him a go-to leader for complex RF and mixed-signal system programs.
9 years of coding experience
5 years of employment as a software developer
Master of Engineering (MEng), Electrical and Electronics Engineering, Master of Engineering (MEng), Electrical and Electronics Engineering at Baylor University
Github Skills (17)
verilog10
sdl10
jes10
pg10
driver10
sys10
fpga10
embedded10
uhd10
system-configuration9
c-language9
hardware9
python9
server-configuration9
cpd9
Programming languages (1)
Github contributions (3)
EttusResearch/fpga
Aug 2017 - Jan 2019
The USRP™ Hardware Driver FPGA Repository
Role in this project:
Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:55 commits in 1 year 5 months
Contributions summary:Daniel focused on low-level FPGA design and configuration within the repository. Their contributions included completing timing constraints and overhauling existing ones. Additionally, the user added support for new hardware revisions (RevC) and made critical changes to the CPLD drive strengths, improving signal integrity.
xilinxlatticeusrphardwarefpga
EttusResearch/uhd
May 2017 - Mar 2019
The USRP™ Hardware Driver Repository
Role in this project:Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:59 commits in 1 year 10 months
Contributions summary:Daniel has primarily worked on bringing up and initializing various components on an EISCAT daughterboard, focusing on the JESD204B link. Their work includes initializing the JESD cores, configuring and resetting the MMCM, and implementing methods for synchronization and control. They also implemented CPLD and LMK chip controls related to clock management, as well as support for phase DAC functionality. Their work suggests a focus on low-level hardware control and interfacing.
driverusrphardwaresdruhd
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.