Deborah Soung
Platform Engineer
San Francisco Bay Area United States
Summary
🤩
Rockstar🎓
Top SchoolDeborah Soung is a Platform Engineer with seven years of experience building scalable hardware design and verification frameworks, primarily using Scala, Chisel, SystemVerilog, C/C++, and Python. At SiFive she has driven platform and verification infrastructure projects—from UPF generation and UNR analysis flows to formal property APIs—while also leading onboarding and testing initiatives for hardware designers. Her open-source contributions to flagship projects like Rocket Chip, Chisel, and FIRRTL include refining HDL compiler phases, improving Verilog emission, and adapting RISC-V test suites for Rocket targets. She pairs hands-on implementation of dynamic memory and ECC models with systems-level thinking about toolchains and emulation, and has a CMU M.S. in ECE and a UC Berkeley B.S. in EECS. A pragmatic collaborator and former Scrum master, she also founded a Gender Diversity Initiative at SiFive, showing a commitment to inclusive engineering culture.
7 years of coding experience
3 years of employment as a software developer
Bachelor of Science - BS, Electrical Engineering and Computer Science (minor in German), Bachelor of Science - BS, Electrical Engineering and Computer Science (minor in German) at University of California, BerkeleyRenewable Energies, Embedded Systems, German Culture, Renewable Energies, Embedded Systems, German Culture at Munich University of Applied SciencesMaster of Science - MS, Electrical and Computer Engineering, Master of Science - MS, Electrical and Computer Engineering at Carnegie Mellon University
Chinese, German
Stackoverflow
61reputation
36reached
1answer
1question
Github Skills (27)
verilog10
assembly10
risc-v10
firrtl10
makefile10
intermediate-code10
scala10
compiler-compiler10
sys10
intermediate-language10
assembler10
chisel10
rt10
compiler10
embedded10
Programming languages (6)
Github contributions (5)
chipsalliance/chisel
Aug 2018 - May 2022
Chisel: A Modern Hardware Design Language
Role in this project:
Backend Developer
Backend DeveloperContributions:129 reviews, 35 commits, 63 PRs in 3 years 9 months
Contributions summary:Deborah focused on enhancements and modifications to the Verilog emitter and ChiselStage within the Chisel hardware design language. They implemented new features, such as the ability to override random values and include before/after initial block macros. Additionally, they worked on fixing issues related to ProtoBuf conversions for Verification IR and other internal code improvements. Their contributions primarily centered around the core infrastructure and compilation aspects of the Chisel project.
rtlasicvhdllanguage-designeda
chipsalliance/rocket-chip
Aug 2018 - Nov 2020
Rocket Chip Generator
Role in this project:Backend Developer
Backend DeveloperContributions:4 reviews, 42 commits, 25 PRs in 2 years 3 months
Contributions summary:Deborah primarily focused on modifying and extending the Rocket Chip Generator, a hardware description language (HDL) compiler. Their contributions involved refining aspects of SRAM annotation and UID assignment within the system, as well as refactoring generator behavior into distinct phases. Furthermore, they contributed to test suite generation and makefile infrastructure.
rtlriscvchipchiselscala
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.