Deepak Jagannath is an experienced ASIC/physical design engineer with 13 years in semiconductor design and verification, currently driving projects at Cadence Design Systems from San Jose. He has deep hands-on expertise across the full RTL-to-GDSII flow including floorplan, placement, CTS, routing, STA, parasitic extraction, DFM and physical verification, and is fluent in Verilog, Spice-based simulation and industry tools like Encounter, Star-RCXT and Virtuoso. His background includes leadership on complex tapeout activities—power planning, timing ECOs, crosstalk/noise analysis and IR checks—gained at Megachips and Kawasaki Microelectronics. Comfortable in Unix environments, he augments physical design skills with scripting (Perl, Tcl, Awk, Sed) to automate flows and improve turnaround. Trained in microelectronics at RMIT and with a BE in electronics, he blends practical layout/schematic intuition with verification rigor. Notably, he brings both low-level CMOS logic understanding and production-grade toolchain fluency, making him effective at resolving cross-domain tapeout challenges.
13 years of coding experience
10 years of employment as a software developer
BE, electronics, BE, electronics at SIT
microelectronics, electronics, microelectronics, electronics at RMIT University Australia
Diamond is a python daemon that collects system metrics and publishes them to Graphite (and others). It is capable of collecting cpu, memory, network, i/o, load and disk metrics. Additionally, it features an API for implementing custom collectors for gathering metrics from almost any source.
Contributions:14 pushes in 4 months
memorypythonprometheusdiamondmonitoring
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Deepak Jagannath - Engineer at Cadence Design Systems