Derui Yang
Associate Professor
Beijing, China
Summary
🤩
Rockstar🎓
Top SchoolDerui Yang is an associate professor and embedded systems engineer based in Beijing with seven years of hands-on experience in low-level systems and IoT development. He contributes to prominent RISC-V Rust projects—notably rustsbi—implementing atomic memory operations and hart management features that improve thread safety and once-initialization for embedded targets. He also documents and refines core OS interfaces in the zCore Zircon reimplementation, clarifying syscall semantics around memory and process management. Blending academic perspective with production-focused contributions, he brings rigorous system-level thinking to open-source projects that sit at the intersection of OS design and embedded Rust.
7 years of coding experience
London School of Economics and Political Science
Github Skills (12)
risc-v10
bare-metal10
rust10
sys10
microkernel10
thread9
multithreading9
process-management9
memory-management9
embedded9
system8
operating-system8
Programming languages (9)
Github contributions (5)
rcore-os/zCore
Mar 2022 - Dec 2022
Reimplement Zircon microkernel in Rust.
Role in this project:
Back-end Developer
Back-end DeveloperContributions:14 reviews, 279 commits, 73 PRs in 9 months
Contributions summary:Derui primarily contributed to the documentation of system calls within the Zircon microkernel reimplementation, specifically focusing on the `vm.rs` and `task.rs` files. These commits involved adding detailed documentation for system calls related to memory management (`sys_mmap`, `sys_munmap`, `sys_mprotect`) and process/thread management (`sys_fork`, `sys_vfork`, `sys_clone`, `sys_wait4`, `sys_execve`). The descriptions include detailed information about the system calls, their arguments, and their behavior.
microkernelrustzirconembeddedreimplement
rustsbi/rustsbi
May 2022 - Aug 2022
RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see https://github.com/rustsbi/prototyper.
Role in this project:Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:9 reviews, 21 commits, 6 PRs in 2 months
Contributions summary:Derui primarily focused on enhancing the `rustsbi/rustsbi` project, a RISC-V SBI library in Rust. Their contributions include implementing AMO (atomic memory operation) instructions for thread safety and once-initialization, crucial for embedded systems. They also fixed critical issues related to hart management, including implementing the `hart_stop` functionality and adapting the project to use the `AmoOnceRef` structure.
bare-metalsbi-specificationrisc-vriscvrust
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