Dmitri Pavlov
HW Engineer at Предприниматель
Russia
Summary
👤
Senior🎓
Top SchoolDmitri Pavlov is a hardware engineer with 15 years’ RTL expertise and a decade of professional experience delivering full-cycle HW IP for ASICs and SoCs. He specializes in Verilog/VHDL/SystemVerilog design, Synopsys DC synthesis flows, FPGA prototyping, and performance characterization, routinely driving architecture exploration through integration and verification. At Syntacore he led RTL development for an open-source RISC-V MCU core, contributing SystemVerilog work on CSRs, exceptions, JTAG/AXI testbenches and timer/memory interfaces. Earlier roles at Intel Labs saw him own DSP engines, microcontroller cores and multiple customer IP derivatives, combining algorithm mapping, RTL implementation and final product integration. As an independent engineer he developed a high-SNR, high-SFDR NCO IP and is currently working on a 64k-point FFT, reflecting deep signal-processing and numeric precision skills. Based in Russia, he blends hands-on RTL craftsmanship with pragmatic system-level verification and integration experience.
10 years of coding experience
18 years of employment as a software developer
High Frequency Communication, High Frequency Communication at Leningrad Energy ColledgeMaster of Science (MSc), Faculty of Computers, computing complexes, systems and networks, Master of Science (MSc), Faculty of Computers, computing complexes, systems and networks at Saint Petersburg State University of Aerospace and Instrumentation
Russian
Stackoverflow
1reputation
0reached
0answers
0questions
Github Skills (14)
rt10
risc-v10
embedded10
verilog10
verification10
formal-verification10
systemverilog10
sys10
hardware10
hardwareid10
axi49
ax9
coreos9
jtag9
Programming languages (4)
Github contributions (5)
syntacore/scr1
May 2017 - Apr 2022
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Role in this project:
Embedded Systems Engineer
Embedded Systems EngineerContributions:42 commits, 3 PRs, 30 pushes in 5 years
Contributions summary:Dmitri primarily focused on low-level hardware interaction and system-level design for the RISC-V MCU core. The commits demonstrate substantial work on SystemVerilog code, including updates to the CSR (Control and Status Registers) module, exception handling, and interrupt management. Their contributions also encompass testbench modifications to incorporate JTAG and AXI interface support, indicating a focus on hardware verification and integration. The user also worked on the timer and memory interface of the core.
risc-vrtlriscvriscv32high-quality
syntacore/fpga-sdk-prj
Dec 2017 - Jan 2022
FPGA-based SDK projects for SCRx cores
Contributions:15 commits, 1 PR, 14 pushes in 4 years 2 months
coressdkfpga
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