Summary
Dmitri Vlasov is a verification engineer and compiler builder with eight years of industry experience and a deep academic background (PhD in algebra and mathematical logic). He develops and verifies FPGA projects using Verilog/SystemVerilog, while also creating functional language tooling and runtime systems informed by prior work on an LLVM-based PHP compiler. Dmitri blends formal methods and practical engineering—proving correctness where possible and increasingly leveraging AI to accelerate both verification and compiler development. His career spans research at the Sobolev Institute through high-load systems at RhythmOne and production compiler/runtime work at Parallels, reflecting comfort across theory and large-scale engineering. Based in Novi Sad, Serbia, he is notable for pairing rigorous mathematical training with hands-on system design, including memory managers, garbage collectors, and associative container algorithms.
8 years of coding experience
18 years of employment as a software developer
Doctor of Philosophy (Ph.D.), Algebra and mathematical logic, Doctor of Philosophy (Ph.D.), Algebra and mathematical logic at Sobolev Institute of Mathematics
Master of Science (MS), mathematics, logic, 4.97, Master of Science (MS), mathematics, logic, 4.97 at Novosibirsk State University (NSU)
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English